The present invention relates generally to semiconductor device manufacturing and, more particularly, to a structure and method for shallow trench isolation (STI) recess repair prior to silicide processing, using a gate spacer layer.
A typical semiconductor device in a complementary metal-oxide-semiconductor (CMOS) circuit is formed in a p-well or an n-well in a semiconductor substrate. Since other semiconductor devices are also present in the semiconductor substrate, a given semiconductor device requires electrical isolation from adjacent semiconductor devices. Electrical isolation is provided by isolation structures that employ trenches filled with an insulator material (e.g., shallow trench isolation or “STI” regions).
In addition, certain inactive areas of a semiconductor device defined by STI regions may also have so called “dummy” gate structures formed thereon. These dummy gate structures on the STI regions are electrically non-functional, but serve one or more mechanical purposes. For example, substantially planar surfaces within a semiconductor topography may play an important role in fabricating overlying layers and structures. That is, step coverage problems may arise when a material is deposited over a surface having raised and recessed regions. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Furthermore, correctly patterning layers upon a surface containing fluctuations in elevation may be difficult using optical lithography.
In general, a topography having relatively wide regions of material may also be more prone to dishing effects of chemical mechanical polishing (CMP) than a topography having relatively narrow regions of material. Thus, the dummy structures formed on the inactive STI regions of a semiconductor device can contribute to a substantially planar surface, but do not affect the functionality of the device.
However, during one or more cleaning processes (e.g., DHF/wet clean/Aqua Regia) used in the front-end-of-the-line (FEOL) processing, the STI regions may be subjected to the formation of severe recesses therein. Such recesses may occur, for example, during metal silicide formation on gate, source and drain contacts of a field effect transistor (FET). Unfortunately, a subsequent cap layer (e.g., nitride) that is formed over the silicided transistor devices can be pinched off so as to have a void formed therein, where such voids correspond to locations above the recessed STI. An STI recess therefore introduces a significant challenge for a middle-of-the-line (MOL) nitride layer to fill the gap between adjacent gates, especially at sub-32 nanometer (nm) ground rules. An incomplete gap fill, also known as a tungsten (W) subway void defect, remains a yield and reliability concern, even on electrically non-functional STI regions.